| 摘要 |
<p>PROBLEM TO BE SOLVED: To maintain constant CPU throughput by measuring the CPU busy rate showing the processing execution state of a processor sequentially and varying the capacity of a cache that the processor has, according to variation in the measured CPU busy rate. SOLUTION: A CPU busy rate measurement unit 3 measures the frequency of access to the cache 2 by a CPU 1 as the CPU busy rate showing the process execution state of the processor. Then, the CPU busy rate measurement unit 3 sends a control signal to the cache 2 to vary the capacity of the cache 2. How many times the control signal is issued, is counted thereafter at a constant time interval until A>=X>=B and set in a latch. The set frequency is compared with a certain frequency which is initially set and the cache control part increases the capacity of the cache 3. Here, A is an upper limit, B is a lower limit, and X is the counted frequency.</p> |
