发明名称 ROUGH WIRING DESIGN METHOD/DEVICE FOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a rough wiring method/and a device with respect to a chip containing various macros. SOLUTION: A hierarchical structure for quartering a chip area hierarchically is constituted by recurrently applying a processing for quartering a rough cell higher by one into four rough cells of 2×2 (step S102). The wiring passing capacity of the high-order rough cell is estimated based on wiring passing capacity calculated on the rough cell in respective hierarchy levels by following the hierarchy level from the low-order one to the high-order one (step S103). A condition on the wiring passing capacity of the respective sides of the high- order rough cell is satisfied in the respective hierarchical levels, the rough wiring route of a net, which is obtained in the high-order hierarchy, is succeeded and the rough wiring route of the passing net of the four rough cells of 2×2 is decided by following the hierarchy level from the high-order one to the low- order one (step S104).
申请公布号 JPH10269258(A) 申请公布日期 1998.10.09
申请号 JP19970069727 申请日期 1997.03.24
申请人 NEC CORP 发明人 FUJII TAKASHI
分类号 H01L21/82;G06F17/50;(IPC1-7):G06F17/50 主分类号 H01L21/82
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