| 摘要 |
PROBLEM TO BE SOLVED: To provide a precise comparison output signal which does not contain a hazard by providing an RS flip flop for inputting a first signal to a set terminal, a second signal to a reset terminal, for inputting the output of an AND gate to a control terminal and for supplying an output signal to a three state buffer. SOLUTION: When the RS flip flop 6 inputs an REF(reference) SET signal to the set (S) terminal, inputs a VAR (comparison) SET signal to the reset (R) terminal and inputs the output signal of the AND gate 6a to the control (CP) terminal, the output signal of the RS flip flop (with gate) 6 becomes the RSQ signal (corresponding output) of a long '1' period. The three state buffer 5 of a post stage becomes gate enable by the EN(enable) signal having the '1' period contained in the '1' period of the RSQ signal and the corresponding period of the RSQ signal is outputted. Thus, '1' period of comparison output (PD) does not contain the hazard and the precise comparison output (PD) signal is obtained. |
