发明名称 RECEPTION CONTROLLER
摘要 PROBLEM TO BE SOLVED: To easily synchronize the frames of received data and to easily establish reception. SOLUTION: The frame synchronizing signal of received data is supplied to a shift register 1, and the data pattern of the frame synchronizing signal is compared with the frame synchronizing signal from the shift register by a comparator 2. An adder circuit 3 performs adding processing while defining a compared output in the case of non-coincidence between the both as a bit error and supplies this result to a decoder 4. Allowable range data showing the allowable range of bit error are supplied through terminals F1 and F0 to the decoder 4, it is detected whether the bit error generated at the time of added output from the adder circuit 3 is settled within the allowable range or not and this result is supplied to a microcomputer. When the detected result showing this bit error is settled within the allowable range is supplied, the microcomputer spriously synchronizes frames and establishes the reception.
申请公布号 JPH10271103(A) 申请公布日期 1998.10.09
申请号 JP19970072102 申请日期 1997.03.25
申请人 YAZAKI CORP 发明人 TSUBAKI KAZUYA;TATARA HIROKAZU
分类号 H04L1/00;H04J3/06;H04L7/08;H04L7/10 主分类号 H04L1/00
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