| 摘要 |
<p>The invention provides a method of combining an EPROM (or EEPROM) with a standard CMOS process. After growing the gate oxide (9), a lightly doped polycrystalline or amorphous silicon layer (10), hereinafter referred to as poly I, is deposited. In this layer, the floating gate (13) of the memory cells is defined, while, outside the memory matrix, the surface remains covered with poly I. Subsequently, the source/drain implantation in the memory cells is carried out. The poly layer (10) situated outside the memory matrix is masked against this heavy implantation by the mask (11). Subsequently, a second poly layer can be provided from which the control gates of the memory cells are formed and which forms a coherent layer with the existing poly I layer outside the matrix. In a subsequent series of steps in a standard CMOS process, the n-ch MOSTs and p-ch MOSTs are provided, n-type gates (22) for the n-ch MOSTs and p-type gates (23) for the p-ch MOSTs being formed from the poly I layer.</p> |
