发明名称
摘要 <p>A device according to the invention (RC) for a time-multiplexed packet switcher (CP) comprises essentially a circuit (B10, B20 to B115, B215, and PO) for detecting the starts and ends of periods of switcher load cutting, and an interval counter (CT). The detection circuit is connected to a plurality of input buffer queues (FA0 to FA15) for the switcher and detects load cutting when all the queues signal an empty-of-packets state. A time base (BT) for the switcher is frozen at the end of an interval, established by the counter, of predetermined duration following detection of a load cutting. The said duration is determined so as to terminate a packet switching in progress. Once the time base is frozen, operation of the switcher is interrupted and its consumption becomes very low. The time base is unfrozen upon reception of a packet by the queues, and the switcher then operates anew. <IMAGE></p>
申请公布号 JP2808650(B2) 申请公布日期 1998.10.08
申请号 JP19890093285 申请日期 1989.04.14
申请人 FURANSU 发明人 SERUBERU MISHERU;BOWAIE PIEERU;KINKI JANNHOORU
分类号 H04B1/16;H04L12/56;(IPC1-7):H04L12/56 主分类号 H04B1/16
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