The memory includes numerous internal supply voltage lines (1,2) generating the internal voltages (VccA,VccP). A column selection signal (SL) is generated at an input/output gate circuit (9a), coupling a bit line pair (BLP) and an internal data line pair (35a,b). The column selection signal is at the same voltage level as the first internal voltage (VccA) applied to a read-out amplifier (6). A current driver capacity of the input/output gate circuit is relatively reduced to a low level so that a rapid potential change of a read-out node of a read-out amplifier is prevented. Thus an inversion of a held data value of the read-out amplifier is prevented in an instance of data collision on the internal data line pair.
