Self-aligned contacts for semiconductor integrated circuits and method for producing the same

摘要

A technique for forming a self-aligned contact in a semiconductor integrated circuit which improves the aspect ratio of the contact by reducing the thickness of the gate stack including the overgate dielectric and the local interconnect oxide layers and which provides a more planar device topography. The resultant contact structure also results in an improved isolation distance between the gate material contact and local polysilicon or polysilicide interconnect layers. The technique disclosed may be utilized in conjunction with the fabrication of memory device integrated circuits and other devices in both matrix and peripheral device elements without degradation of circuit performance.