| 摘要 |
1,082,106. Circuit assemblies. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 13, 1965 [Dec. 23, 1964], No. 43344/65. Heading H1R. In an integrated circuit comprising a plurality of devices 3 formed in co-ordinate array on a P-type semi-conductor wafer 1, interconnections are formed by groups of first conductors 7, and groups of second conductors 11 insulated therefrom by a layer of insulation 13, connections between selected conductors 7, 11 being effected by lateral extensions 17 which extend from conductors 11 through holes 15 in insulating layer 13. Devices 3 may comprise single active or passive components or solid-state circuits, and are provided with a plurality of terminals 5 formed by degenerately - doped diffusions or deposited metal. Lower conductors 7 are formed by a degeneratelydoped diffused N-type pattern; alternatively, a layer of dielectric is thermally grown on the surface of wafer 1 and conductors 7 are formed by vapour deposition of a layer of metal, e.g. Al, followed by photo-etching. Selected conductors such as 7a, 7b are shorter than other conductors in their respective groups. Insulating layer 13 is applied by thermal oxidation or, when deposited metal conductors 7 are employed, by vapour deposition, pyrolitic deposition, or sputtering. Holes 15, in coordinate array as shown, or only where required for a specific circuit, are formed in insulating layer 13 by photo-etching; then upper conductors 11 are formed, together with conductive connections between terminals 5 and conductors 7, and power and ground leads 19, 21, by vapour depositing a metallic film over layer 13, followed by photo-etching of the film. In a modification, Fig. 2 (not shown), in which the lower conductors (7) are formed by deposition, the insulating layer is replaced by discrete insulating strips (13) lying transverse to the lower conductors (7) and bearing upper conductors (11, 21 &c.). |
