发明名称 |
Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory |
摘要 |
In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.
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申请公布号 |
US5818782(A) |
申请公布日期 |
1998.10.06 |
申请号 |
US19970814507 |
申请日期 |
1997.03.10 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO.LTD. |
发明人 |
KOTANI, HISAKAZU;AKAMATSU, HIRONORI;NAKAO, ICHIRO;YAMADA, TOSHIO;SAWADA, AKIHIRO;KIKUKAWA, HIROHITO;AGATA, MASASHI;IWANARI, SHUNICHI |
分类号 |
G11C5/02;G11C7/10;G11C11/4096;(IPC1-7):G11C13/00 |
主分类号 |
G11C5/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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