| 摘要 |
For a semiconductor circuit having one or more semiconductor devices, such as an IGBT, a turn-ON prevention circuit is provided for each device which prevents the device from turning ON during OFF times thereof, due to the presence of a transient voltage (dV/dt) across the main terminals of the device. In accordance with such a scheme, a MOSFET is connected between the insulated-gate electrode and emitter of the IGBT, and a capacitor, for example, is connected between the gate of the MOSFET and a sufficient electric potential to thereby effect a temporary turn-ON of the MOSFET to remove parasitic charge build-up in the IGBT before such charge build-up has reached a potential of the turn-ON threshold of the IGBT during OFF times of the IGBT. The capacitance element can be constituted by a MOSFET, namely, the capacitance across the gate-to-drain of an additional MOSFET. As a result, therefore, power consumption can be kept sufficiently small and the chip area required for implementing the circuit, such as, in a monolithic construction can be reduced. Further, the turn-ON prevention scheme can be applied to MOSFET devices rather than IGBTs.
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