发明名称 Method for forming multileves interconnections for semiconductor fabrication
摘要 A method for forming interconnections for semiconductor fabrication and semiconductor devices have such interconnections are described. A first patterned dielectric layer is formed over a semiconductor substrate and has a first opening filled with conductive material. Another patterned dielectric layer is formed over the first dielectric layer and has a second opening over at least a portion of the conductive material. The first patterned dielectric layer may serve as an etch-stop in patterning the other patterned dielectric layer. Also, a dielectric etch-stop layer may be formed over the first patterned dielectric layer and over the conductive material before the other patterned dielectric layer has been formed. This dielectric etch-stop layer may serve as an etch-stop in patterning the other patterned dielectric layer. The second opening exposes a portion of the dielectric etch-stop layer. The exposed portion of the dielectric etch-stop layer is removed. The second opening is filled with conductive material.
申请公布号 US5817572(A) 申请公布日期 1998.10.06
申请号 US19960768790 申请日期 1996.12.18
申请人 INTEL CORPORATION 发明人 CHIANG, CHIEN;FRASER, DAVID B.
分类号 H01L21/768;H01L23/522;H01L23/532;(IPC1-7):H01L21/44 主分类号 H01L21/768
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