| 摘要 |
A fractional N-frequency synthesizer includes an accumulator outputting an output value, and a spurious signal cancel circuit. The spurious signal cancel circuit includes a pulse forming circuit, receiving a spurious signal cancelling reference signal, a reset signal and the output value of the accumulator, and outputting, in synchronism with the spurious signal cancelling reference signal, a pulse voltage signal having a pulse width proportional to the output value of the accumulator from a time when the reset signal is received, and a constant current circuit controlled by the pulse voltage signal and outputting an output current of the spurious signal cancel circuit.
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