发明名称 |
Processor for performing shift operations on packed data |
摘要 |
A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a fist location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data shift operation is to be performed. The processor further includes a circuit being coupled to the decoder. The circuit is for shifting a first packed data being stored at the first location by a value being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.
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申请公布号 |
US5818739(A) |
申请公布日期 |
1998.10.06 |
申请号 |
US19970840245 |
申请日期 |
1997.04.17 |
申请人 |
INTEL CORPORATION |
发明人 |
PELEG, ALEXANDER;YAARI, YAAKOV;MITTAL, MILLIND;MENNEMEIER, LARRY M.;EITAN, BENNY |
分类号 |
G06F7/00;G06F5/01;G06F7/76;G06F9/30;G06F9/315;G06F9/38;(IPC1-7):G06F5/01 |
主分类号 |
G06F7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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