发明名称 Video decoder engine
摘要 MPEG compressed video data is decompressed in a computer system by sharing computational decompression tasks between the computer system host microprocessor, the graphics accelerator, and a dedicated MPEG processor (video decoder engine) in order to make best use of resources in the computer system. Thus the dedicated MPEG processor is of minimum capability and hence advantageously minimum cost. The host microprocessor is used to decompress the MPEG upper data layers. The more powerful the host microprocessor, the more upper data layers it decompresses. The remainder of the decompression (lower data layers) is performed by the MPEG dedicated processor and/or the graphics accelerator. The video decoder engine is a fast hardwired processor. It has a graceful degradation capability to allow dropping of occasional video frames without displaying any part of a dropped video frame. The video decoder engine has a three stage pipeline structure to minimize circuitry and speed up operation.
申请公布号 US5818967(A) 申请公布日期 1998.10.06
申请号 US19950490322 申请日期 1995.06.12
申请人 S3, INCORPORATED 发明人 BHATTACHARJEE, SOMA;STEARNS, CHARLES C.
分类号 G06T9/00;H04N5/00;H04N7/26;H04N7/50;H04N7/52;(IPC1-7):G06K9/00;G06K9/36;G06K9/46;G06K9/54 主分类号 G06T9/00
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