Static ram with reduced power consumption

摘要

The invention relates to a memory comprising a matrix of memory cells; a plurality of gates for transmitting respective selection outputs of a row decoder to respective rows of the matrix; a dummy bit line having an equivalent load as bit lines associated to columns of the matrix and which is discharged by a dummy memory cell when any row is selected; and circuitry for precharging the bit lines and the dummy bit line when no row is selected, and enabling said gates for transmission of the selection outputs of the row decoder in response to a clock signal. Each gate has an input coupled to the dummy bit line such that the gate is disabled as soon as the dummy bit line has discharged to a switching threshold of the gate.