发明名称 |
Look-up table using multi-level decode |
摘要 |
A look-up table circuit implemented with MOS transistors that uses combinational logic to generate signals that enable the transistors. A circuit using 16 inputs and 4 select lines is disclosed. Two of the select lines are used as inputs to combinational logic including four NOR gates to generate enable signals for transistors in a third stage of the circuit. This produces a reduction in the propagation delay of a signal from the input to the output of the look-up table circuit.
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申请公布号 |
US5815024(A) |
申请公布日期 |
1998.09.29 |
申请号 |
US19970833363 |
申请日期 |
1997.04.04 |
申请人 |
ALTERA CORPORATION |
发明人 |
REDDY, SRINIVAS T.;GUPTA, ANIL |
分类号 |
H03K17/00;H03K17/693;(IPC1-7):H03K17/62 |
主分类号 |
H03K17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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