| 摘要 |
PCT No. PCT/US95/00295 Sec. 371 Date Jul. 10, 1996 Sec. 102(e) Date Jul. 10, 1996 PCT Filed Jan. 10, 1995 PCT Pub. No. WO95/19046 PCT Pub. Date Jul. 13, 1995A circuit architecture is disclosed wherein power is supplied to a CMOS circuit through a first pair of voltage rails, including a first voltage rail (12) providing a first voltage and a second voltage rail (14) providing a second voltage, and a second pair of voltage rails, including a third voltage rail (16) providing a third voltage and a fourth voltage rail (18) providing a fourth voltage. Components (20, 22) comprising two circuit portions are connected across either the first or second pair of voltage rails. The voltage difference across each pair of voltage rails is less than the threshold voltage of the groups of component (20, 22) so that very little current is drawn. Because the voltage offset between the first and second pairs of rails is greater than the threshold voltage of the groups of components (20, 22), sufficient voltage is provided for switching. Circuitry may be provided for monitoring the voltage of one of the rails to insure that its value provides the proper off current and for biasing both the substrate and wells to compensate for variations amongst components. The four rail architecture of the present invention may be combined with a Class B output buffer or the four rail circuit itself may be designed as a Class B circuit to reduce power consumption.
|
