| 摘要 |
PROBLEM TO BE SOLVED: To obtain video data with high stability by reading out video data out of a memory in timing of an input synchronizing signal. SOLUTION: A PLL circuit 2 generates a write clock WCK in phase with an input HD and a write signal AHD by dividing the frequency of WCK to control the memory 1 through a write control part 3 and write video data, and the memory 1 is controlled with the signal from a readout timing signal generation part 4 through a readout control part 5 to read the video data out. A readout timing signal generation part 4 oscillates a read clock RCK by using a crystal oscillator, etc., divides the frequency of RCK to generate a horizontal readout timing signal FHD, and counts RCK to reset counter with input VD, thereby generating a vertical readout timing signal FVD. The counter is reset on counting up to the cycles of the vertical synchronizing signal pulseα, and generates FVD with the set value when there is not the input VD.
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