| 摘要 |
An integrated circuit and method produce a first clock signal (CLOCK) from a reference clock (REFCLK) but at a different frequency. A variable delay line (32) produces the first clock signal by introducing a variable delay in the reference clock signal that is controlled by a programming signal generated in a counter (34). The programming signal is incremented by a second clock signal (UP) while transitions of a fixed delay clock signal lead transitions of the first clock signal. When the programming signal reaches the count of a rollover code (ROLLOVER), the programming signal is reset to a zero count to begin a new sequence. A calibration circuit (36, 38, 40, 42) determines the count of the programming signal needed to produce the rollover code when the variable delay is at least as great as one period of the reference clock signal.
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