| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a highly versatile clock transfer control circuit, without the need for difficult timing design capable of coping, even with the change of the frequency ratio of internal clocks and external clocks. SOLUTION: This circuit is provided with a shift register 3 for shifting delayed external clocks, for which the external clocks are delayed by the internal clocks and a combination logic circuit 35 for generating the timing control signals of the pulse width of one cycle of the internal clocks of the same frequency as the external clocks for all the values for which the integer N is scheduled of the frequency ratio. In such a manner, since the timing control signals are generated, corresponding to all the values for which the integer N is scheduled of the frequency ratio in the combination logic circuit, even the change in the frequency ratio is coped with, versatility is improved, and the need of the difficult timing design is eliminated as well.</p> |
