Bit map addressing schemes for flash memory

摘要

Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. "By-address" architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.