System for handling interrupts in a computer system using asic reset input line coupled to set of status circuits for presetting values in the status circuits

摘要

The present invention provides an interrupt register for handling interrupt requests received from external devices at a common interrupt terminal of a CPU. The invention provides inputs, outputs, and storage means as part of the interrupt register. The interrupt register inputs and outputs are used for communication with both the external devices and CPU to prevent mishandling of the interrupt requests.