| 摘要 |
PROBLEM TO BE SOLVED: To increase an operation speed of a synchronous SRAM and the like provided with a sense amplifier drive timing control section, to reduce its testing man-hours, and to reduce a manufacturing cost. SOLUTION: A test mode which is selectively specified by making a phase comparison disenable signal TPD supplied from an input terminal TPD an effective level is provided in a synchronous SRAM and the like. Also, in a sense amplifier drive timing control section SADC, a counter control signal CC for synchronizing-operating an up-down counter U/DC is formed based on a clock signal CK, that is, an internal clock signal CK1 at the time of an operation mode, and it is formed based on a test clock signal TCK supplied from an input terminal TCK at the time of a test mode. Further, an up signal UP or a down signal DN for counting up or counting down the up/down counter U/DC is formed conforming to an up signal up or a down signal dn outputted from a phase comparison circuit PC at the time of a normal operation mode, and it is formed conforming to a phase control signal TPC supplied from an input terminal TPC at the time of a test mode. |
