发明名称 |
MICROPROCESSOR AND DATA PROCESSING SYSTEM |
摘要 |
<p>PROBLEM TO BE SOLVED: To provide the microprocessor which can minimize a decrease in data processing efficiency or an increase in power consumption because of refreshing operation. SOLUTION: The microprocessor 1 which has a CPU 2 and DRAMs(dynamic RAM) 6 to 9 on a chip has a DRAM controller 10 which inhibits the DRAMs 6 to 9 from being refreshed individually according to control information set by the CPU 2. When refreshing operation is not needed like a period wherein data are processed while the DRAMs are accessed regularly and successively exceeds a refreshment interval, no interruption for refreshing operation is initiated halfway during the data processing by canceling the refreshing operation of the DRAMs, thereby suppressing a decrease in data processing efficiency or an increase in the power consumption resulting from unnecessary refreshing operation.</p> |
申请公布号 |
JPH10260950(A) |
申请公布日期 |
1998.09.29 |
申请号 |
JP19970062791 |
申请日期 |
1997.03.17 |
申请人 |
HITACHI LTD |
发明人 |
NARITA SUSUMU;AYUKAWA KAZUSHIGE |
分类号 |
G11C11/406;G06F15/78;(IPC1-7):G06F15/78 |
主分类号 |
G11C11/406 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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