| 摘要 |
There is provided a DRAM using a low electric power consumption characteristic of a VCC/2 precharging method and capable of performing stable and high speed sensing operation even under a low power supply voltage condition. The DRAM has a memory cell array, a plurality of word lines, a plurality of bit line pairs, sense amplifiers disposed to correspond to the bit line pairs, a first precharge circuit for precharging the bit line pairs in the first group of two groups obtained by dividing the plural bit line pairs to a first precharge potential between +E,fra 1/2+EE of power supply voltage Vcc and the ground potential, a second precharge circuit for precharging the bit line pairs in the second group to a second precharge potential which is higher than Vcc/2 by a degree corresponding to the difference between Vcc/2 and the first precharge potential and a precharge control circuit for causing the first and second precharge circuits to sequentially perform corresponding precharge operations with the time difference.
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