| 摘要 |
<p>PROBLEM TO BE SOLVED: To execute the data processing of high performance while the reference clock of a prescribed frequency is generated without being affected by the frequency fluctuation of a data transfer clock supplied through an extension bus by variably setting the frequency of the reference clock in accordance with the fluctuation of the data transfer clock supplied through the extension bus. SOLUTION: A control signal (f) is connected to a PLL circuit 2 from a micro computer 6 and control for setting the frequency-dividing ratio of a frequency-dividing circuit in the PLL circuit 2 and the like can be executed. The PLL circuit 2 frequency-divides the data transfer clock (a) supplied through the extension bus and generates the reference clock (b) synchronized with the data transfer clock (a). The frequency of the data transfer clock (a) is measured by the inner timer of the micro computer 6. The frequency of the reference clock (b), which the PLL circuit 2 generates, based on the measured frequency, is set by the control signal (f) setting the frequency-dividing ratio from the micro computer 6.</p> |
