Double word line decoder circuit for DRAM memory cells

摘要

The circuit includes numerous lower word lines (SWL), associated with several memory cells (Cell 1.1 - Cell 4.N), that each have a driver (34A,B) energised by a signal (RA1,2) for energising an allocated pair of main word lines (MWL,MWLB). A decoder (31,32) transmits the lower word line energising signal to the driver at a specified level. The level concerns an earth voltage (VSS) and a first raised voltage level (VPP2), higher than a positive power supply voltage level (VDD) according to an applied, inverted precharge signal (PCB) and applied first address signal (AX5,6), and changes accordingly. A main word line energiser (33) energises the first word line of the pair according to specified criteria, while the second main word line is energised, depending on stated conditions.