CLOCK SIGNAL DISTRIBUTING METHOD

摘要

PROBLEM TO BE SOLVED: To minimize skew and to generate and distribute a clock signal by inspecting the adequacy of data of a data bus by a memory controller by using a copy of the clock signal. SOLUTION: For writing to a memory module 76, a memory controller 74 generates the clock signal to be propagated along a 1st clock line segment. To read data, a copy of the clock when supplied by a 2nd clock line segment is propagated in the reverse direction in the 1st clock line segment from the memory module 76 along a loop and reaches the memory controller 74 along the 2nd clock line segment. At this time, electric characteristics of the data bus and clock line segments are matched so that incident wave fronts of the data bus and clock signal reach the memory controller 74 while having mutually constant relation.