发明名称 |
Biasing scheme for reducing stress and improving reliability in EEPROM cells |
摘要 |
<p>Disclosed is a method for biasing dual row line EEPROM cells. The new biasing scheme improves the data retention lifetime of an EEPROM cell by reducing the potential difference between the control gate and the write column of the cell, which reduces the tunnel oxide electric field. In a preferred embodiment, the method involves applying bias voltages to the control gate and write column of an EEPROM cell such that the potential difference between the control gate and the right column is no more than about 0.6 volts. By biasing the cell's write column to a positive voltage, the tunnel oxide field may be significantly reduced. Moreover, the invention provides a method of selecting a write column voltage based on a control gate voltage such that the tunnel oxide field is substantially balanced in all its modes. This biasing scheme minimizes stress-induced leatiage current (SILC) and improves cell reliability.</p> |
申请公布号 |
EP0866466(A2) |
申请公布日期 |
1998.09.23 |
申请号 |
EP19980302112 |
申请日期 |
1998.03.20 |
申请人 |
ALTERA CORPORATION |
发明人 |
MADURAWE, RAMINDA U.;SANSBURY, JAMES D.;SMOLEN, RICHARD G.;TURNER, JOHN E.;LIANG, MINCHANG;COSTELLO, JOHN C.;WONG, MYRON W. |
分类号 |
H01L29/788;H01L29/792;G11C16/04;G11C16/26;G11C29/50;H01L21/8247;H01L27/115;(IPC1-7):G11C16/04;G11C16/06 |
主分类号 |
H01L29/788 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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