Apparatus for coordinating clock oscillators in a fully redundant computer system

摘要

A redundant computer system including two systems capable of independent operation. The two systems correspondingly employ two independent clock generation and distribution (CGD) units which each issue clock and clock definer signals. When the two systems are split, each system is controlled by the oscillator signal generated by its own CGD unit. When the two systems are merged, one oscillator is designated as master, and its output is employed to derive the clock and definer signals on both sides of the redundant system. Special logic included in each CGD unit ensures that the change from master to slave (or slave to master) operation is performed without error. This special logic includes circuitry which places a temporary hold at a predetermined logic level on the local oscillator signal, which is in use when the switch is made, when the local clock and definer signals are both at the predetermined logic level. The hold continues until the oscillator which is to "take over" is also at the predetermined logic level.