发明名称 |
Method of fabricating deep submicron MOSFET with narrow gate length using thermal oxidation of polysilicon |
摘要 |
The present invention relates to forming a narrow gate MOSFET having a local ion implantation to reduce the junction capacitance. A polysilicon layer is formed over a semiconductor substrate. An opening is formed in the polysilicon layer by using patterning and etching. Subsequently, a thermal oxidation is performed to oxidize the polysilicon layer into a polysilicon-oxide layer that is expanded in volume relative to the polysilicon layer thereby narrowing said opening. Then an ion implantation is performed by using said polysilicon-oxide layer as a mask.
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申请公布号 |
US5811339(A) |
申请公布日期 |
1998.09.22 |
申请号 |
US19960712148 |
申请日期 |
1996.09.11 |
申请人 |
VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
TSENG, HORNG-HUEI |
分类号 |
H01L21/28;H01L21/336;(IPC1-7):H01L21/336 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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