发明名称
摘要 PURPOSE:To reduce an irregularity in erasing characteristic between memory cells, to increase repetitively rewritable times and to enhance its reliability by alleviating an electric field generated between a source region and the end of a floating gate electrode at the time of applying an erasing voltage. CONSTITUTION:Electric field alleviating means for alleviating an electric field generated between a source region 10 and the end 5E of a floating gate electrode 5 at the time of application of an erasing voltage is provided by forming the end 5e of the electrode 5 obtuse. Accordingly, the concentration of an applying electric field at the end 5E of the electrode 5 at the time of erasing is avoided, and the tunnel emission of electrons is conducted at a flat part isolated from the end 5E of the electrode 5. Thus, an irregularity in erasing characteristic between memory cells is reduced, repetitively rewritable times can be increased, and high reliability is obtained.
申请公布号 JP2799711(B2) 申请公布日期 1998.09.21
申请号 JP19880114420 申请日期 1988.05.10
申请人 发明人
分类号 G11C17/00;H01L21/28;H01L21/8247;H01L27/105;H01L27/115;H01L29/423;H01L29/788;H01L29/792;(IPC1-7):H01L21/824 主分类号 G11C17/00
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