| 摘要 |
The present invention concerns a DBS receiver which serves to combine the functions of variable rate demodulation, convolutional decoding, de-interleaving and block decoding. The demodulation stage includes a novel circuit for clock synchronization. By combining the functions of these components this device provides a higher level of utility as measured in terms of reliability, simplicity, flexibility, cost effectiveness, and integration of board layout while maintaining optimum-quality signal processing. |
