ELASTIC BUS INTERFACE DATA BUFFER

摘要

An elastic bus interface receives and registers an external data transfer signal (28) and generates an internal data transfer signal (44) that always begins at the beginning of the subsequent clock cycle regardless of the time of arrival of the external data transfer signal. By employing a plurality of data output registers (54, 56) in a pipeline and using only the internal data transfer signal, data is fed to a bus (25) so as to ensure that almost a complete clock cycle is available for setup time to accomplish data transfer. The invention can operate with high speed buses using only simple conventional circuitry and modest process geometries requiring only minimal chip area and power.