| 摘要 |
PCT No. PCT/JP96/02143 Sec. 371 Date Mar. 12, 1997 Sec. 102(e) Date Mar. 12, 1997 PCT Filed Jul. 30, 1996 PCT Pub. No. WO97/06600 PCT Pub. Date Feb. 20, 1997A rational frequency division device eliminates spurious components by a simple arrangement and can set a broad frequency modulation range. A frequency synthesizer using the rational frequency division device includes an arithmetic circuit, which outputs the frequency division ratio to a frequency divider in a PLL circuit constituted by a variable frequency oscillator 4, a frequency divider 6, and a phase detector 2. The arithmetic circuit includes a plurality of series-connected cumulative adders 22 which include a first cumulative adder that receives a rational number defined by an integer value and a decimal value, an integer value extraction circuit 23 for extracting an integer value from the output value of the cumulative adder of the final stage, and a delay circuit 24 for outputting the integer value extracted by the integer value extraction circuit to the frequency divider as the frequency division ratio, and outputting the integer value to the respective cumulative adders as a feedback value. Each cumulative adder adds a value calculated by itself in the previous clock period to the input rational number or the output value from the cumulative adder of the previous stage, and subtracts the feedback value from the delay circuit therefrom, thus outputting the calculated value.
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