| 摘要 |
Improved jitter performance is realized in a desynchronizer for obtaining an asynchronous signal, e.g., a Conference of European Posts and Telecommunicati ons (CEPT)-4 signal, from a received synchronous signal, e.g., a Synchronous Digital Hierarchy (SDH) Synchronous Transport Module (STM)-1 signal. The improved jitter performance results from employing a unique gap generator which causes gaps in a received data signal to be spread regularly in time, and allows for almost conti nuous control by numerical techniques of the phase of a smooth output clock being gene rated. Phase control is obtained by employing a filtered version of the difference betw een the actual number of data bits in the received digital signal and the expected nomin al number.
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