发明名称 System and method for zeroing pages with cache line invalidate instructions in an LRU system having data cache with time tags
摘要 A check is made to determine if a copy of a cache line is currently resident in the level-one data cache of a microprocessor system. If, in response to the check, it is determined that a copy of such cache line in fact is not currently resident, the cache line is created as the least-recently used cache line. Then, for set-associative data caches, the next used of the associative set will replace the most recently zeroed line. In this way, zeroing operations can replace only one DIVIDED (number of associative sets) of the data cache for zeroing operations, thereby leaving the most frequently used data intact. By doing so, the data-cache is not wasted on zeroed cache lines which may be infrequently reused from the data cache, thereby significantly improving system performance. In other words the net effect is to reduce probability of data cache misses on subsequent instructions because more of the cache is thereby made available for more frequently reused data. The state of the cache is better preserved without creating performance losses exhibited by the previous technique. In a preferred embodiment, the hereinbefore described system and method is employed in systems with processors comprising substantial writeback queues and memory subsystems permitting numerous outstanding writes to be in progress, and is further employed in systems embodying cache line zero/invalidate instructions.
申请公布号 US5809548(A) 申请公布日期 1998.09.15
申请号 US19960706053 申请日期 1996.08.30
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 CHANG, JOSEPH YIH;OLSZEWSKI, BRET RONALD
分类号 G06F12/12;(IPC1-7):G06F12/12 主分类号 G06F12/12
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