发明名称 Reconfiguring control system in a parallel processing system by replacing an error-detected processing unit
摘要 A sender processor unit 101 transmits a packet to which a logical address of a receiver processor unit is added. Network routers 102 to 108 obtains a physical address corresponding to a destination logical address by referring to a processor address translation table 122 through a signal line 140, sets a route 112 and transfers the packet to a receiver processor unit 107. When a fault is caused in the receiver processor unit 107, a service processor changes correspondence of logical addresses to physical addresses of the processor address translation table 122. Consequently, a route 113 to a substitute processor unit 105 is dynamically
申请公布号 US5808886(A) 申请公布日期 1998.09.15
申请号 US19950403998 申请日期 1995.03.14
申请人 HITACHI, LTD. 发明人 SUZUKI, KAORU
分类号 G06F15/16;G05B19/18;G06F12/10;G06F15/173;G06F15/177;G06F15/80;(IPC1-7):G05B19/18 主分类号 G06F15/16
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