发明名称 Purge control for ON-chip cache memory
摘要 A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instructioon is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output the instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
申请公布号 US5809274(A) 申请公布日期 1998.09.15
申请号 US19970886464 申请日期 1997.07.01
申请人 HITACHI, LTD.;HITACHI MICRO COMPUTER ENGINEERING, LTD. 发明人 NISHIMUKAI, TADAHIKO;HASEGAWA, ATSUSHI;UCHIYAMA, KUNIO;KAWASAKI, IKUYA;HANAWA, MAKOTO
分类号 G06F9/30;G06F9/312;G06F9/34;G06F9/345;G06F9/38;G06F9/445;G06F12/00;G06F12/02;G06F12/08;G06F12/10;G06F12/12;G06F13/16;G06F15/78;(IPC1-7):G06F9/312 主分类号 G06F9/30
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