发明名称 |
Dual bus system with multiple processors having data coherency maintenance |
摘要 |
A multi-module network having dual system busses using a common bus protocol which supports processor modules using a store-through cache memory and processor modules using a non-store-through cache memory which includes interface modules including a spy unit for maintaining cache coherency and arbiter modules so that any particular module is not starved out. A maintenance processor organizes the network as a joined system where both the store-through and non-store through processor units can utilize either one of the dual system busses or a split system where one bus is dedicated to the store-through processor units and one bus is dedicated to the non-store through processor units.
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申请公布号 |
US5809533(A) |
申请公布日期 |
1998.09.15 |
申请号 |
US19970797216 |
申请日期 |
1997.02.11 |
申请人 |
UNISYS CORPORATION |
发明人 |
TRAN, DAN TRONG;RICCI, PAUL BERNARD;SHETH, JAYESH VRAJLAL;WHITE, THEODORE CURT;COWGILL, RICHARD ALLEN |
分类号 |
G06F13/42;(IPC1-7):G06F13/16 |
主分类号 |
G06F13/42 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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