| 摘要 |
A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an arithmetic logic unit connected to the memory, operative to perform an arithmetic operation on data received by the arithmetic unit. An instruction decode and control unit connected to the memory, having an instruction register operative to hold a program instruction, is operative to decode a program instruction providing control signals to control the operations of the data processing device and to initiate a interrupt sequence responsive to an instruction code having a interrupt instruction. A program sequencer circuit connected to the memory, having a program register operative to hold a program counter corresponding to a program address is operative to access the memory with the program register to obtain the program instruction corresponding to the program address. A interrupt handler unit, connected to the instruction decode and control unit and the memory, having a hold register operative to store the program register, responsive to the control signals from the instruction decode and control unit to generate an intermediate address to access an interrupt counter from the memory, is operative to store the program register into the hold register and replace the program register with the interrupt counter wherein the interrupt counter corresponds to an address for accessing an interrupt instruction to execute an interrupt routine stored in the memory. Other devices, systems and methods are also disclosed.
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