DIGITAL DATA DEMODULATING APPARATUS

摘要

In a digital data demodulating apparatus, a sampling circuit samples a received signal at a speed N x K(N > 1, K > l; integers) times a symbol rate to output received signal sequences. N received signal sequence selection circuits estimate channel impulse responses from the respective received signal sequences to obtain channel state data, and output a control pulse and the estimated channel impulse response values. A received signal sequence selection controller outputs a switch control signal on the basis of the channel state data. N selectors select demodulation received signal sequence candidates from the received signal sequences on the basis of the control pulse. A first switch selects/outputs a received signal sequence to be demodulated on the basis of the switch control signal. A second switch selects/outputs an estimated channel impulse response value estimated from the received signal sequence to be demodulated on the basis of the switch control pulse. A demodulation circuit performs demodulation upon reception of the outputs from the first and second switches.