| 摘要 |
PROBLEM TO BE SOLVED: To shorten the intervals of word lines by connecting diffused layers to conductor layers using the first and second conductor layers connecting bit lines or node electrodes to respective diffused layers through the intermediary of the second vertical wirings as well as bit or node contact holes in the self- matching structure with respective diffused layers. SOLUTION: The first node contact hole 118 and the first bit contact hole 110 are self-matchingly structured respectively with a node diffused layer 107 and a bit diffused layer 108. In such a constitution, the intervals of work lines 104 can be shortened by providing the first and second conductor layers 111, 112 on the upper side of the word lines 104 covered with a CVD silicon oxide film while the intervals of bit lines 116 can be also shortened by providing the second bit contact hole 114, the first vertical wiring 115, the second node contact hole 118 and the second vertical wiring 119 thereby enabling the space of the title memory cell to be narrowed. |
