CLOCK DRIVER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

摘要

PROBLEM TO BE SOLVED: To obtain a clock driver circuit having high driving ability and small clock skew at the time of both normal operation and testing operation. SOLUTION: The clock driver circuit comprises first and second clock drivers 15a, 15b. In the drivers 15a, 15b, a plurality of main drivers 19(1) to 19(n) are connected at input nodes to a first common line 18 and at output nodes to a second common line 21. The line 21 is connected to a plurality of clock signal supply lines 20(1) to 20(m). A plurality of clock signal supply lines 21(1) to 21(m) are connected to a clock input node of a second macro cell 16 requiring for a clock signal. The lines 18a, 21a of the driver 15a are respectively electrically connected to the lines 18b, 21b of the driver 15b via first and second connecting means 22 at the time of a test mode.