| 摘要 |
<p>PROBLEM TO BE SOLVED: To transmit data without error at a high rate without increasing power consumption and generating unnecessary radiation by having a data- transmission-use successive clock generation circuit for generating a successive clock of an optimal frequency. SOLUTION: It is not until /XCK rises that an output Q1 of a reset circuit 7 does not becomes high, and then, a frequency divider 8 starts frequency- dividing, and outputs a data-transmission-use successive clock CLK with a half frequency of a data-read-use successive clock DCLK connected with a clock input terminal ck2 . Thereafter, since the output of the reset circuit 7 remains high unless a start signal ENHAVDD falls to Low, a frequency divider 8 continues frequency-dividing to output the data-transmission-use successive clock CLK continuously. At this time, the frequency divider 8 starts frequency- dividing in synchronization with a rise of /XCK, therefore, the rise of the data- transmission-use successive clock CLK, output of the frequency divider 8, and that of an intermittent shift clock XCK are always synchronized with each other.</p> |
