| 摘要 |
PROBLEM TO BE SOLVED: To reduce the parasitic capacitance of data lines by placing ground- power wirings mutually parallel and approximately orthogonally to word lines not overlapped therewith on wiring layers separate from data lines and placing common contact holes at approximately centers of memory cells but contact holes at approximately end parts. SOLUTION: Ground wirings 19, 20 and power wiring 21 are formed with separate wiring layers from data lines 26, 27 in memory cells and are mutually approximately parallel and orthogonal to word lines 3, 4. Data lines 26, 27 are disposed above and below these wirings 19, 20, 21 and hence no parallel plate parasitic capacitance is formed between the upper and lower data lines. Common contact holes 15, 16 connected to one end of a load element and power wiring 21 are disposed at approximately centers of the memory cells while contact holes connected to source regions of driving transistors and ground wiring are disposed at approximately their ends to which the work lines 3, 4 extend. |
