| 摘要 |
<p>PROBLEM TO BE SOLVED: To remove a useless space and to reduce a chip area by arranging a whole circuit block except for first and second row decoders and cell arrays between the first and second cell array groups. SOLUTION: The first cell array group 10 has a plurality of cell arrays 10a and the second cell array group has a plurality of cell arrays 11a. The first and second cell array groups 10 and 11 are arranged in parallel. The first row decoder 12a is provided for the first cell array group 10 and the second row decoder 12b for the second cell array group 11. The whole circuits except for the first and second row decoders 12a and 12b and the cell array groups 10 and 11, which are reset transistors 13a and 13b, Y selectors 14a and 14b, first layer metal wirings 20a and 20b and the like, are concentrically arranged on an area positioned between the first and second cell array groups 10 and 11.</p> |
