| 摘要 |
PROBLEM TO BE SOLVED: To easily form wirings between logic parts and memories by providing multilayer logic wiring groups, memory wiring groups, scribe region wiring and below-terminal wiring and interconnecting the wiring groups to connect the logic parts and memories. SOLUTION: Surface wirings 5, 15 of logic parts 1 and memories 2 are composed of wirings 5a, 15a constructing a first through sixth layers, conductive plugs 5b, 15b extending in a direction Z for connecting the upper and lower wirings 5a, 15a, and conductive plugs 5c, 15c for connecting the wirings 5a, 15a to semiconductor regions 45 on the surface layer of a semiconductor substrate 6 of the logic parts 1 and memories 2. Multilayer wiring structured wiring groups 3 are provided at the periphery and surface and formed on the surface of the substrate 6 having no element such as transistor and hence the no. of layers of the wirings on the parts 1 and memories 2 is equal to that of the multilayer wirings between the parts, it is planarized to facilitate the wiring work. |
