| 摘要 |
PROBLEM TO BE SOLVED: To accurately reproduce a transmitted data signal even when the phase delay of a data signal exceeds the variable delay limit of a synchronizing circuit. SOLUTION: When one of synchronizing(SYN) circuits 18a, 18b to be two systems detects that a data signal 1 reaches the delay limits of SYN clocks 17a, 17b, the other system switches the SYN clock of one system to the SYN clock of the other system synchronizing with a phase advanced from the SYN clock of one system, and when one system detects that its SYN clock reaches its advance limit due to the advance of the data signal 1, the other system switches the SYN clock to the SYN clock of the other system synchronized with a phase delayed from the SYN clock of one system so as to synchronize with the data signal 1 and the data signal 1 is reproduced by a synchronized identification clock 11. |
